? semiconductor components industries, llc, 2002 april, 2002 rev. 4 1 publication order number: mc10e171/d mc10e171, mc100e171 5vecl 3bit 4:1 multiplexer the mc10e/100e171 contains three 4:1 multiplexers with differential outputs. separate select controls are provided for the leading 2:1 mux pairs (see logic symbol). the three select inputs control which one of the four data inputs in each case is propagated to the corresponding output. the 100 series contains temperature compensation. ? 725 ps max. d to output ? split select ? differential outputs ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 2 kv hbm, > 200 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 203 devices device package shipping ordering information mc10e171fn plcc28 37 units/rail mc10e171fnr2 plcc28 500 units/reel mc100e171fn plcc28 37 units/rail mc100e171fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e171fn awlyyww mc100e171fn awlyyww 128 128 http://onsemi.com
mc10e171, mc100e171 http://onsemi.com 2 d 0 bd 0 cd 0 dv cco v cco d 2 a d 2 b d 2 c d 2 d d 1 a d 1 dd 0 a d 1 b sel1a sel1b sel2 v ee nc nc d 1 c 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 567 8910 q 2 q 2 v cc q 1 q 1 v cco q 0 q 0 1 pinout: 28-lead plcc (top view) * all v cc and v cco pins are tied together on the die. logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. pin description pin function d 0 xd 2 x ecl data inputs sel1a, sel1b ecl first-stage select inputs sel2 ecl second-stage select input q 0 q 2 ecl true output q 0 q 2 ecl inverted output v cc , v cco positive supply v ee negative supply nc no connect function table pin state operation sel2 h output c/d data sel1a h input d data sel1b h input b data logic diagram d 0 a d 0 b d 0 c d 0 d d 1 a d 1 b d 1 c d 1 d d 2 a d 2 b d 2 c d 2 d sel1a sel1b sel2 q 0 q 0 q 1 q 1 q 2 q 2 2:1 mux sel 2:1 mux sel 2:1 mux sel 2:1 mux sel 2:1 mux sel 2:1 mux sel 2:1 mux sel 2:1 mux sel 2:1 mux sel
mc10e171, mc100e171 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 56 67 56 67 56 67 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 56 67 56 67 56 67 ma v oh output high voltage (note 2) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 2) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc10e171, mc100e171 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 56 67 56 67 65 77 ma v oh output high voltage (note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 56 67 56 67 65 77 ma v oh output high voltage (note 2) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh propagation delay to output ps t phl d 275 480 650 275 480 650 275 480 650 sel1 450 650 850 450 650 850 450 650 850 sel2 350 550 700 350 550 700 350 550 700 t skew within-device skew (note 1.) ps dnm, dnm to qn 60 60 60 da, db, dc, dd to q 40 40 40 t jitter cycletocycle jitter tbd tbd tbd ps t r rise/fall time ps t f (20 - 80%) 300 475 650 300 475 650 300 475 650 1. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. 1. within-device skew is defined as identical transitions on similar paths through a device; n = 0,1,2 m = a,b,c,d.
mc10e171, mc100e171 http://onsemi.com 5 figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e171, mc100e171 http://onsemi.com 6 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.004 (0.100) seating plane -t- 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum t, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). view s b u z g1 x view d-d h k f view s g c z a r e j 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc -n- y brk d d w -m- -l- 28 1 v g1 k1
mc10e171, mc100e171 http://onsemi.com 7 notes
mc10e171, mc100e171 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e171/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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